Effect of dual three-phase configurations and interleaved carrier-based PWM techniques on the DC-Link current stress

Dual Three-Phase (DTP) winding configurations are gaining importance in automotive powertrains, where the DC-Link capacitor plays a critical role in terms of power density and reliability, as it accounts for approximately 40% of the inverter's volume and about 30% of its failures. This work systematically analyses the influence of various DTP configurations (S0-DTP, A30-DTP, S60-DTP) and DTP-specific Double Zero-Sequence Injection (DZSI) PWM techniques on the DC-Link capacitor current spectrum to minimize its RMS value. Using the Double Fourier Integral formalism, this work derives analytical expressions for input current harmonics, identifies dominant ripple components, and assesses interleaving strategies to suppress these harmonics, thereby reducing RMS current stress on the capacitor. The findings are validated through experimental measurements, which confirm that proper selection of DZSI-PWM techniques and interleaving angles leads to up to 85% reduction in capacitor RMS current stress compared to standard non-interleaved modulation, thus enhancing power converter reliability without additional hardware modifications. These insights offer practical design guidelines for electric vehicle powertrains and high-performance multiphase inverters.