Ahmed, H. orcid.org/0000-0001-8952-4190, Rahoui, A. orcid.org/0000-0002-2619-2472 and Ahmad, S. orcid.org/0000-0002-2958-1131 (2026) Equivalence-based tuning of ADRC- and SRF-PLLs for grid-connected systems. IEEE Transactions on Consumer Electronics. p. 1. ISSN: 0098-3063
Abstract
AC-DC power conversion is fundamental to grid-connected consumer technology, where phase-locked loops (PLLs) are typically used for real-time parameter estimation. This paper demonstrates that a linear active disturbance rejection control (ADRC)-based PLL is dynamically equivalent to a conventional synchronous reference frame (SRF)-PLL equipped with an inloop low-pass filter (LPF). This equivalence is established analytically through small-signal modeling and parameter mapping. Using bandwidth-parameterization-based tuning for the ADRC-PLL, equivalent proportional-integral (PI) control gains and LPF cut-off frequency for the SRF-PLL are derived analytically, while the inverse mapping–including cases based on the symmetric optimum method–is performed numerically by solving a third-order polynomial equation. Theoretical findings are validated through experimental results using a grid-connected AC-DC PWM rectifier. When tuned under equivalent conditions, both PLLs exhibit nearly identical dynamic performance. Experimental tests under non-ideal grid conditions reveal a performance trade-off: the ADRC-PLL offers greater robustness to high-order harmonics, whereas the SRF-PLL demonstrates superior performance under low-order distortion and voltage unbalance. These results provide a unified framework linking ADRC and SRF-PLL formulations, supporting the design of advanced PLL architectures that combine the strengths of both approaches.
Metadata
| Item Type: | Article |
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| Authors/Creators: |
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| Copyright, Publisher and Additional Information: | © 2026 The Authors. Except as otherwise noted, this author-accepted version of a journal article published in IEEE Transactions on Consumer Electronics is made available via the University of Sheffield Research Publications and Copyright Policy under the terms of the Creative Commons Attribution 4.0 International License (CC-BY 4.0), which permits unrestricted use, distribution and reproduction in any medium, provided the original work is properly cited. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/ |
| Keywords: | Phase locked loops; Tuning; Frequency; Gain; Timing; Modeling; Voltage; Filtering; Filters; Transfer functions |
| Dates: |
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| Institution: | The University of Sheffield |
| Academic Units: | The University of Sheffield > Faculty of Engineering (Sheffield) > School of Electrical and Electronic Engineering |
| Date Deposited: | 09 Jun 2026 13:37 |
| Last Modified: | 09 Jun 2026 13:37 |
| Status: | Published |
| Publisher: | Institute of Electrical and Electronics Engineers (IEEE) |
| Refereed: | Yes |
| Identification Number: | 10.1109/tce.2026.3695711 |
| Sustainable Development Goals: | |
| Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:241850 |
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