Xia, H. orcid.org/0009-0003-0361-2520, Wang, S., Zhao, Y. et al. (3 more authors) (2025) A high accuracy and hardware efficient approximate computing based leaky integrate-and-fire neuron model. In: 2025 IEEE 38th International System-on-Chip Conference (SOCC). 38th IEEE International System-on-Chip Conference, 29 Sep - 01 Oct 2025, Dubai, United Arab Emirates. Institute of Electrical and Electronics Engineers (IEEE). ISBN: 9798331594794. ISSN: 2164-1676. EISSN: 2164-1706.
Abstract
The adoption of Spiking Neural Networks (SNNs) has grown significantly, driven by their potential to enhance image processing, robotics, and motor control. These applications typically demand both high performance and low power consumption, especially when deployed on edge devices. Achieving high-performance and low-power SNNs in hardware remains challenging due to their computational complexity and large-scale design. Balancing accuracy and speed often increases power and resource usage, making efficient implementation essential. Optimizing a single neuron model—a fundamental unit replicated thousands of times—is key to improving overall hardware efficiency. The Leaky Integrate-and-Fire (LIF) model, widely used in SNNs, offers a more efficient alternative to other neuron models by improving computational and energy efficiency. This paper presents a LIF neuron model design based on approximate multiplication. Given the high robustness of SNNs, they are well-suited for approximate computing. The proposed design significantly reduces multiplication complexity with only 2.6099% error. The minimal error has little impact on SNN performance, as shown by similar training results between approximate and precise LIF-based SNNs across various datasets and network sizes. To further demonstrate the advantages of our AM-based LIF neuron model, we carry on a test through a Xilinx FPGA. The FPGA implementation results demonstrate that the AM-based LIF neuron achieves a 8.26% to 84.36% reduction in Look-Up Table utilization, a 17.04% to 86.49% reduction in slice register utilization, and achieving a 10.31-fold increase in energy efficiency relative to the state-of-the-art LIF neuron model.
Metadata
| Item Type: | Proceedings Paper |
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| Authors/Creators: |
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| Copyright, Publisher and Additional Information: | © 2025 The Authors. Except as otherwise noted, this author-accepted version of a proceedings paper published in 2025 IEEE 38th International System-on-Chip Conference (SOCC) is made available via the University of Sheffield Research Publications and Copyright Policy under the terms of the Creative Commons Attribution 4.0 International License (CC-BY 4.0), which permits unrestricted use, distribution and reproduction in any medium, provided the original work is properly cited. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/ |
| Keywords: | Training; Accuracy; Computational modeling; Neurons; Approximate computing; Spiking neural networks; Hardware; Energy efficiency; Table lookup; Field programmable gate arrays |
| Dates: |
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| Institution: | The University of Sheffield |
| Academic Units: | The University of Sheffield > Faculty of Engineering (Sheffield) > Department of Electronic and Electrical Engineering (Sheffield) The University of Sheffield > Faculty of Engineering (Sheffield) > School of Electrical and Electronic Engineering |
| Date Deposited: | 05 Jan 2026 12:36 |
| Last Modified: | 05 Jan 2026 12:36 |
| Status: | Published |
| Publisher: | Institute of Electrical and Electronics Engineers (IEEE) |
| Refereed: | Yes |
| Identification Number: | 10.1109/socc66126.2025.11235406 |
| Related URLs: | |
| Sustainable Development Goals: | |
| Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:235945 |
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