Khattak, F. A. and Mikaitis, M. orcid.org/0000-0001-8706-1436 (2025) Generalized Methodology for Determining Numerical Features of Hardware Floating-Point Matrix Multipliers: Part I. In: Proceedings of 2025 IEEE High Performance Extreme Computing Conference (HPEC). 29th Annual IEEE High Performance Extreme Computing Virtual Conference, 15-19 Sep 2025, Online. . IEEE. ISBN: 979-8-3315-7844-2. ISSN: 2643-1971. EISSN: 2643-1971.
Abstract
Numerical features of matrix multiplier hardware units in NVIDIA and AMD data centre GPUs have recently been studied. Features such as rounding, normalisation, and internal precision of the accumulators are of interest. In this paper, we extend the methodology for analysing those features, to consumer-grade NVIDIA GPUs by implementing an architecture-independent test scheme for various input and output precision formats. Unlike current approaches, the proposed test vector generation method neither performs an exhaustive search nor relies on hard-coded constants that are device-specific, yet remains applicable to a wide range of mixed-precision formats. We have applied the scheme to the RTX-3060 (Ampere architecture), and Ada RTX-1000 (Ada Lovelace architecture) graphics cards and determined numerical features of matrix multipliers for binary16, TensorFloat32, and bfloat16 input floating point formats and binary16 and binary32 IEEE 754 output formats. Our methodology allowed us to determine that the numerical features of RTX-3060, a consumer-grade GPU, are identical to those of the A100, a data centre GPU. We do not expect our code to require any changes for performing analysis of matrix multipliers on newer NVIDIA GPUs, Hopper or Blackwell, and their future successors, and any input/output format combination, including the latest 8-bit floating-point formats.
Metadata
| Item Type: | Proceedings Paper |
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| Authors/Creators: |
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| Copyright, Publisher and Additional Information: | This is an author produced version of a proceedings paper published in Proceedings of 2025 IEEE High Performance Extreme Computing Conference (HPEC), made available under the terms of the Creative Commons Attribution License (CC-BY), which permits unrestricted use, distribution and reproduction in any medium, provided the original work is properly cited. |
| Dates: |
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| Institution: | The University of Leeds |
| Academic Units: | The University of Leeds > Faculty of Engineering & Physical Sciences (Leeds) > School of Computing (Leeds) |
| Funding Information: | Funder Grant number EPSRC Accounts Payable OPP136 |
| Date Deposited: | 10 Sep 2025 09:21 |
| Last Modified: | 21 Apr 2026 14:26 |
| Status: | Published |
| Publisher: | IEEE |
| Identification Number: | 10.1109/HPEC67600.2025.11196657 |
| Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:231310 |
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