Betha, H.V., Odavic, M. orcid.org/0000-0002-2104-8893 and Atallah, K. orcid.org/0000-0002-8008-8457 (2023) Analytical modelling of SiC MOSFET based on datasheet parameters considering the dynamic transfer characteristics and channel resistance dependency on the drain voltage. In: 2023 IEEE Applied Power Electronics Conference and Exposition (APEC). 2023 IEEE Applied Power Electronics Conference and Exposition (APEC), 19-23 Mar 2023, Orlando, FL, USA. Institute of Electrical and Electronics Engineers (IEEE) , pp. 90-95. ISBN 9781665475389
Abstract
Silicon Carbide devices enable high power density power electronic converters due to their lower junction capacitances and higher thermal conductivity. Analytical models of these devices help in estimating the switching dynamics, losses and current/voltage stresses on the devices. The dynamics of SiC MOSFET current during turn ON is impacted by the drain voltage it is switched at, due to the drain induced barrier lowering (DIBL) effect. This is however ignored in the existing analytical models available in the literature. This paper thus proposes and develops a new analytical modelling approach that models this effect by relying only on the datasheet parameters, thereby avoiding the need for expensive and time-consuming experimental methods. Dynamic channel resistance is also modelled as a function of drain voltage. The analysis reveals the impact of drain voltage on damping time of high frequency drain current oscillations during turn ON. An experimental double pulse test (DPT) setup using 1.2kV SiC MOSFET (C3MOOI0602K) and Schottky diode (C4D40120D) is built to verify the findings. Further, the accuracy of the proposed model is compared against the most detailed existing model in the literature.
Metadata
Item Type: | Proceedings Paper |
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Authors/Creators: |
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Copyright, Publisher and Additional Information: | © 2023 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Reproduced in accordance with the publisher's self-archiving policy. |
Keywords: | Drain induced barrier lowering; SiC MOSFET; double pulse test; switching loss; analytical model |
Dates: |
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Institution: | The University of Sheffield |
Academic Units: | The University of Sheffield > Faculty of Engineering (Sheffield) > Department of Electronic and Electrical Engineering (Sheffield) |
Depositing User: | Symplectic Sheffield |
Date Deposited: | 05 Mar 2024 16:56 |
Last Modified: | 13 Jun 2024 15:29 |
Status: | Published |
Publisher: | Institute of Electrical and Electronics Engineers (IEEE) |
Refereed: | Yes |
Identification Number: | 10.1109/apec43580.2023.10131160 |
Related URLs: | |
Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:209946 |