Yang, P, Wang, Q, Guo, T et al. (2 more authors) (2018) Adaptive Optimization Design of Vector Error Diffusion Algorithm and IP Core for FPGA. In: Proceedings - 2018 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation. 2018 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation, 08-12 Oct 2018, Guangzhou, China. IEEE , pp. 1193-1198. ISBN 978-1-5386-9380-3
Abstract
A vector error diffusion algorithm can obtain better halftone results than a scalar error diffusion algorithm in digital printing, thus, extensive research work about the vector error diffusion has been done to decrease the time that users wait for printing. In this paper, an improved vector error diffusion IP core is proposed. The IP is implemented in FPGA and can meet the requirement of real-time printing by the improvements as follow: three R G B planes are computed in parallel, a matrix-valued error filter is designed to diffuse error among the three planes, matrix-valued pre-stored memory is created to speed multiplications and five stage pipelines are adopted to replace traditional sequential processes. Based on the improvements, we build a practical hardware test system on the SoCKit platform. The test results show that optimal algorithm only needs one clock circle to get the halftone result of a pixel on average and can meet the requirements of practical printing.
Metadata
Item Type: | Proceedings Paper |
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Authors/Creators: |
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Copyright, Publisher and Additional Information: | © 2018 IEEE. This is an author produced version of a paper published in Proceedings - 2018 IEEE SmartWorld, Ubiquitous Intelligence & Computing, Advanced & Trusted Computing, Scalable Computing & Communications, Cloud & Big Data Computing, Internet of People and Smart City Innovation. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. Uploaded in accordance with the publisher's self-archiving policy. |
Keywords: | Vector error diffusion; FPGA |
Dates: |
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Institution: | The University of Leeds |
Academic Units: | The University of Leeds > Faculty of Engineering & Physical Sciences (Leeds) > School of Electronic & Electrical Engineering (Leeds) > Robotics, Autonomous Systems & Sensing (Leeds) |
Depositing User: | Symplectic Publications |
Date Deposited: | 08 Feb 2019 15:40 |
Last Modified: | 11 Feb 2019 12:14 |
Status: | Published |
Publisher: | IEEE |
Identification Number: | 10.1109/SmartWorld.2018.00208 |
Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:142337 |