Ultrasound array transmitter architecture with high timing resolution using embedded phase-locked loops

Coarse time quantization of delay profiles within ultrasound array systems can produce undesirable sidelobes in the radiated beam profile. The severity of these sidelobes is dependent upon the magnitude of phase quantization error - the deviation from ideal delay profiles to the achievable quantized case. This paper describes a method to improve inter channel delay accuracy without increasing system clock frequency by utilising embedded Phase-Locked Loop (PLL) components within commercial Field Programmable Gate Arrays (FPGAs). Precise delays are achieved by shifting the relative phases of embedded PLL output clocks in 208 ps steps. The described architecture can achieve the necessary inter element timing resolution required for driving ultrasound arrays up to 50 MHz. The applicability of the proposed method at higher frequencies is demonstrated by means of extrapolating experimental results obtained using a 5 MHz array transducer. Results indicate an increase in Transmit Dynamic Range (TDR) when using accurate delay profiles generated by the embedded PLL method described, as opposed to using delay profiles quantized to the system clock.