Gate-oxide degradation in SiC MOSFETs: common-mode noise as a precursor, theoretical basis, and experimental validation

Gate oxide degradation is one of the dominant chip-level failure mechanisms in silicon carbide (SiC) mosfets and poses a major challenge for the long-term reliability of power electronic converters. Conventional precursors such as threshold-voltage shift, Miller plateau variation, and gate leakage current provide useful information about oxide health but typically require intrusive measurements or dedicated test intervals. This article, for the first time, investigates common-mode (CM) conducted noise as a nonintrusive, system-level precursor for gate oxide degradation in SiC mosfets. An analytical framework is first developed to link trap-induced shifts in threshold and Miller plateau voltages to changes in the switching transients and the resulting CM displacement current. The model predicts an asymmetric evolution of the drain-source voltage slopes, with a faster turn-offtransition and a slower turn-on transition as degradation progresses. These effects are shown to reshape both the time-domain CM waveform and the envelope of its frequency spectrum.The analysis in this article is validated experimentally using two discrete SiC mosfets from different manufacturers. Devices are aged by the high-electric-field-stress method, while the gate waveforms, switching transients, and CM noise are measured through a line impedance stabilization network setup. The results confirm that the CM noise amplitude and spectral content exhibit clear, monotonic trends with degradation and are consistent across both device technologies. These findings establish CM noise as a practical, nonintrusive precursor for online condition monitoring of SiC mosfet gate-oxide degradation.