A residue number system-based bit-exact Izhikevich neuron architecture for high-throughput neuromorphic hardware

Spiking Neural Networks enable energy-efficient computation through event-driven processing. The Izhikevich neuron model provides rich firing dynamics but requires quadratic operations that rely on multipliers and limit hardware efficiency, while existing multiplier-free implementations introduce approximation errors that accumulate over time and alter firing behaviour. To address this, this work proposes a multiplier-free and bit-exact neuron architecture based on the Residue Number System (RNS), where all multiplications are replaced by precomputed lookup tables and threshold comparison is performed using an efficient RNS-based sign detection method. The design guarantees bit-for-bit equivalence to the binary INT16 reference at every time step. Validation at both neuron and network levels shows zero numerical deviation from INT16 and negligible accuracy difference from FP32. On a 28 nm AMD Zynq-7020 FPGA, the design achieves 417 MHz and 417M neuron updates/s with zero DSP usage, delivering a 2.4 × frequency improvement over a binary INT16 baseline on the same platform. ASIC synthesis in TSMC 28 nm reaches 3.33 GHz and 3.33G neuron updates/s, corresponding to a 3.83\times improvement in frequency and throughput over the prior LLSMu-based design on the same technology node and representing the highest reported throughput for Izhikevich neuron implementations.