A ultra-low cost and accurate AMC algorithm and its hardware implementation

Automatic Modulation Classification (AMC) is one of the most important applications in the SDR field, which requires both accuracy and critical real-time processing. To address the challenges of speed and accuracy, this article presents a low-cost, and accurate AMC algorithm and its FPGA implementation that can achieve both fast and accurate results at the same time. This work focuses on achieving high accuracy at high SNRs and acceptable accuracy at low SNRs in a short processing time with extremely low power and recourse consumption. In this design, the CAMC algorithm is optimized to fit the FPGA characteristics to further improve the performance, and the computing demands of which could be saved over 94% compared with other state-of-the-art designs. Meanwhile, the CAMC FPGA implementation could save over 82% of the resource utilization and over 94% of the power consumption while a higher accuracy of 56% at 0 dB and 100% above 6 dB could still be performed at a 9.74x faster speed compared with the fastest AMC FPGA design so far.