A passive filter for mitigating neutral-point voltage stress in inverter-fed drives

The short turn ON/OFF time and high switching frequencies of the SiC semiconductor devices can lead to several problems such as over-voltage at the machine terminal and in machine windings, increased electromagnetic interference (EMI), and bearing currents. Past studies and standards have proposed numerous EMI filters to mitigate these issues. However, these filters are designed to mitigate the over-voltage at the machine terminals and do not address potentially excessive voltage stress at the star neutral point of a 3-phase winding and may even aggravate this voltage stress. A mathematical model reveals that the voltage stress at the neutral point results from the superposition of voltage waves traveling in different phases. This study proposes an analytical approach, based on impedance measurement, to select the optimal parameters of a cost-effective passive filter to reduce voltage oscillations at the neutral point. Detailed experimental validation is presented showing the benefits of the proposal while resulting in only minimal added losses. Also, the performance of the proposed filter is compared with a commercial dV/dt filter. It is shown that the proposed filter can be used in conjunction with conventional filters to effectively suppress the voltage stress at all locations and reduce conducted EMI.