PCB busbar optimization for distributed DC link capacitors and parallel discrete SiC MOSFETs

Commutation loop inductance is critical in the design of high-power density power electronic converters that employ fast switching Silicon Carbide (SiC) MOSFETs as it impacts the losses and voltage/ current stresses of the devices and thereby the overall reliability of the converter. This inductance is influenced by the DC link busbar layout and the relative placement of the DC link capacitors and power devices. In this paper, a distributed DC link capacitor layout strategy that minimizes the commutation loop inductance is investigated. The principle of flux cancellation is utilized in designing the PCB busbar board. The layout scheme is analyzed using ANSYS Q3D and the resulting inductance contributed by the DC link to the commutation loop is estimated. The above analysis is validated both through simulations and double pulse test results. Additionally, the arrangement of paralleled power devices in a half bridge is analyzed using ANSYS Q3D with the objective of improving the current sharing.