Chang, Wanli orcid.org/0000-0002-4053-8898, Goswami, Dip, Chakraborty, Samarjit et al. (3 more authors) (2017) Memory-aware embedded control systems design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. pp. 586-599. ISSN 0278-0070
Abstract
Control applications are often implemented on highly cost-sensitive and resource-constrained embedded platforms, such as microcontrollers with a small on-chip memory. Typically, control algorithms are designed using model-based approaches, where the details of the implementation platform are completely ignored. As a result, optimizations that integrate platform-level characteristics into the control algorithms design are largely missing. With the emergence of cyber-physical systems (CPS)-oriented thinking, there has lately been a strong interest in co-design of control algorithms and their implementation platforms, leading to work on networked control systems and computation-aware control algorithms design. However, there has so far been no work on integrating the characteristics of a memory architecture into the design of control algorithms. In this paper we, for the first time, show that accounting for the impact of on-chip memory (or cache) reuse on the performance of control applications motivates new techniques for control algorithms design. This leads to significant improvement in quality of control for given resource availability, or more efficient implementations of embedded control applications. We believe that this paper opens up a variety of possibilities for memory-related optimizations of embedded control systems, that will be pursued by researchers working on computer-aided design for CPS.
Metadata
Item Type: | Article |
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Authors/Creators: |
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Copyright, Publisher and Additional Information: | © 2016 IEEE. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details. |
Keywords: | Embedded control systems,memory analysis,nonuniform sampling,quality of control (QoC) |
Dates: |
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Institution: | The University of York |
Academic Units: | The University of York > Faculty of Sciences (York) > Computer Science (York) |
Depositing User: | Pure (York) |
Date Deposited: | 24 Aug 2020 08:30 |
Last Modified: | 01 Feb 2025 00:07 |
Published Version: | https://doi.org/10.1109/TCAD.2016.2613933 |
Status: | Published |
Refereed: | Yes |
Identification Number: | 10.1109/TCAD.2016.2613933 |
Related URLs: | |
Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:164760 |