Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management
Kelefouras, V, Keramidas, G and Voros, N
(2017)
Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management.
In:
IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017).
ISVLSI 2017, 03-05 Jul 2017, Bochum, Germany.
IEEE
, pp. 477-482.
ISBN 9781509067626
Abstract
In this paper, we present a new methodology that provides i) a theoretical analysis of the two most commonly used approaches for effective shared cache management (i.e., cache partitioning and loop tiling) and ii) a unified framework to fine tuning those two mechanisms in tandem (not separately). Our approach manages to lower the number of main memory accesses by one order of magnitude keeping at the same time the number of arithmetical/addressing instructions in a minimal level. We also present a search space exploration analysis where our proposal is able to offer a vast deduction in the required search space.
Metadata
Item Type:
Proceedings Paper
Authors/Creators:
Kelefouras, V
Keramidas, G
Voros, N
Copyright, Publisher and Additional Information:
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