Trefzer, Martin Albrecht orcid.org/0000-0002-6196-6832, Lawson, David Michael Renwick, Bale, Simon Jonathan et al. (2 more authors) (2017) Hierarchical Strategies for Efficient Fault Recovery on the Reconfigurable PAnDA Device. IEEE Transactions on Computers. 7756359. pp. 930-945. ISSN 0018-9340
Abstract
A novel hierarchical fault-tolerance methodology for reconfigurable devices is presented. A bespoke multi-reconfigurable FPGA architecture, the programmable analogue and digital array (PAnDA), is introduced allowing fine-grained reconfiguration beyond any other FPGA architecture currently in existence. Fault blind circuit repair strategies, which require no specific information of the nature or location of faults, are developed, exploiting architectural features of PAnDA. Two fault recovery techniques, stochastic and deterministic strategies, are proposed and results of each, as well as a comparison of the two, are presented. Both approaches are based on creating algorithms performing fine-grained hierarchical partial reconfiguration on faulty circuits in order to repair them. While the stochastic approach provides insights into feasibility of the method, the deterministic approach aims to generate optimal repair strategies for generic faults induced into a specific circuit. It is shown that both techniques successfully repair the benchmark circuits used after random faults are induced in random circuit locations, and the deterministic strategies are shown to operate efficiently and effectively after optimisation for a specific use case. The methods are shown to be generally applicable to any circuit on PAnDA, and to be straightforwardly customisable for any FPGA fabric providing some regularity and symmetry in its structure.
Metadata
Item Type: | Article |
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Authors/Creators: |
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Copyright, Publisher and Additional Information: | © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. |
Keywords: | Circuit faults,Computer architecture,Routing,Field programmable gate arrays,Maintenance engineering,Transistors,Fabrics,FPGA,Special-Purpose and Application-Based Systems,Performance of Systems,Reconfigurable Computing Architectures,Reconfigurable Hardware,Fault tolerance |
Dates: |
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Institution: | The University of York |
Academic Units: | The University of York > Faculty of Sciences (York) > Electronic Engineering (York) |
Funding Information: | Funder Grant number EPSRC EP/I005838/1 |
Depositing User: | Pure (York) |
Date Deposited: | 17 Jan 2017 16:55 |
Last Modified: | 21 Jan 2025 17:24 |
Published Version: | https://doi.org/10.1109/TC.2016.2632722 |
Status: | Published |
Refereed: | Yes |
Identification Number: | 10.1109/TC.2016.2632722 |
Related URLs: | |
Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:110643 |