Gomony, Manil Dev, Garside, Jamie, Akesson, Benny et al. (2 more authors) (2017) A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems. IEEE Transactions on Computers. 7523935. pp. 212-225. ISSN 0018-9340
Abstract
Embedded systems are increasingly based on multi-core platforms to accommodate a growing number of applications, some of which have real-time requirements. Resources, such as off-chip DRAM, are typically shared between the applications using memory interconnects with different arbitration polices to cater to diverse bandwidth and latency requirements. However, traditional centralized interconnects are not scalable as the number of clients increase. Similarly, current distributed interconnects either cannot satisfy the diverse requirements or have decoupled arbitration stages, resulting in larger area, power and worst-case latency. The four main contributions of this article are: 1) a Globally Arbitrated Memory Tree (GAMT) with a distributed architecture that scales well with the number of cores, 2) an RTL-level implementation that can be configured with five arbitration policies (three distinct and two as special cases), 3) the concept of mixed arbitration policies that allows the policy to be selected individually per core, and 4) a worst-case analysis for a mixed arbitration policy that combines TDM and FBSP arbitration. We compare the performance of GAMT with centralized implementations and show that it can run up to four times faster and have over 51 and 37 percent reduction in area and power consumption, respectively, for a given bandwidth.
Metadata
Item Type: | Article |
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Authors/Creators: |
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Copyright, Publisher and Additional Information: | Copyright © 2016 IEEE. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details. |
Keywords: | GAMT,globally arbitrated memory tree,latency-rate servers,mixed-time-criticality,Real-time systems,scalability,shared memory |
Dates: |
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Institution: | The University of York |
Academic Units: | The University of York > Faculty of Sciences (York) > Computer Science (York) |
Funding Information: | Funder Grant number EPSRC EP/K011626/1 |
Depositing User: | Pure (York) |
Date Deposited: | 06 Dec 2016 14:36 |
Last Modified: | 23 Jan 2025 00:09 |
Published Version: | https://doi.org/10.1109/TC.2016.2595581 |
Status: | Published |
Refereed: | Yes |
Identification Number: | 10.1109/TC.2016.2595581 |
Related URLs: | |
Open Archives Initiative ID (OAI ID): | oai:eprints.whiterose.ac.uk:109069 |
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