Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip

Harbin, James orcid.org/0000-0002-6479-8600 and Soares Indrusiak, Leandro orcid.org/0000-0002-9938-2920 (2016) Comparative performance evaluation of latency and link dynamic power consumption modelling algorithms in wormhole switching networks on chip. Journal of systems architecture. pp. 33-47. ISSN 1383-7621

Abstract

Metadata

Item Type: Article
Authors/Creators:
Copyright, Publisher and Additional Information:

© 2016, Elsevier. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details

Keywords: Dynamic power consumption,Network on chip,NoC modelling,Simulation models,TLM,Transaction level modelling
Dates:
  • Published: 1 February 2016
  • Published (online): 22 January 2016
  • Accepted: 13 January 2016
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Computer Science (York)
The University of York
Funding Information:
Funder
Grant number
EPSRC
EP/J003662/1
Depositing User: Pure (York)
Date Deposited: 07 Jun 2016 13:53
Last Modified: 06 Feb 2025 00:06
Published Version: https://doi.org/10.1016/j.sysarc.2016.01.002
Status: Published
Refereed: Yes
Identification Number: 10.1016/j.sysarc.2016.01.002
Related URLs:
Open Archives Initiative ID (OAI ID):

Download

Export

Statistics