On the effect of SiC power MOSFET gate oxide degradation in high frequency phase leg-based applications

Silicon Carbide power MOSFET is a promising option for high power high density applications in the next generation of power electronic applications. Investigating the reliability issues and concerns, however, is a pre-requisite for enabling this technology to be widely used. Gate oxide degradation is a major chip-related failure mode in MOSFETs. The problem of gate oxide degradation is even more severe in SiC MOSFETs because of the thin gate-oxide layer. Interface trapped charge at SiCSiO2 interface is much higher than Si counterpart. The main effect of gate oxide degradation is changes in Miller plateau and threshold voltage value of the switch. These changes usually lead to having a longer rise time and shorter fall time in the switch. Although extensive research has been carried out on proposing precursors and characterization for SiC MOSFET gate oxide degradation, a circuit-level study is lacking. In this paper, the effect of gate oxide degradation on the operation of a half-bridge converter is studied. It is shown that the deadtime between the high side and low side switches in phase leg structure has been increased. In high frequency applications with short pulsewidth, the main consequence is that the average load voltage will be decreased. To show the effect of gate oxide degradation on phase leg operation, simulation in PSpice and experimental set-up are used. Commercial discrete SiC MOSFET 650V/22A is degraded in gate oxide layer using an adjustable degradation set-up. The brand-new and degraded switches are examined in a phase leg structure with switching frequency of 115kHz. The results showed that a 45% increment in deadtime is detected, which leads to decrement in the average voltage of the load.