C-NNAP - A parallel processing architecture for binary neural networks

Kennedy, J.V., Austin, J. orcid.org/0000-0001-5762-8614, Pack, R. et al. (1 more author) (1995) C-NNAP - A parallel processing architecture for binary neural networks. In: Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE , New York , pp. 1037-1041.



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  • Published: 1995
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Computer Science (York)
Depositing User: Repository Assistant
Date Deposited: 03 Jan 2007
Last Modified: 07 Dec 2022 08:54
Published Version: https://doi.org/10.1109/ICNN.1995.487564
Status: Published
Publisher: IEEE
Refereed: No
Identification Number: https://doi.org/10.1109/ICNN.1995.487564
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