Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects

Wang, Haitong, Audsley, Neil C. orcid.org/0000-0003-3739-6590 and Chang, Wanli orcid.org/0000-0002-4053-8898 (2020) Addressing resource contention and timing predictability for multi-core architectures with shared memory interconnects. In: Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020. 26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020, 21-24 Apr 2020 Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS . Institute of Electrical and Electronics Engineers Inc. , AUS , pp. 70-81.

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Copyright, Publisher and Additional Information: This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details.
Keywords: Engineering
Dates:
  • Accepted: 28 February 2020
  • Published: April 2020
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Computer Science (York)
Depositing User: Pure (York)
Date Deposited: 24 Feb 2020 09:50
Last Modified: 16 Nov 2021 01:14
Published Version: https://doi.org/10.1109/RTAS48715.2020.00-16
Status: Published
Publisher: Institute of Electrical and Electronics Engineers Inc.
Series Name: Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS
Refereed: No
Identification Number: https://doi.org/10.1109/RTAS48715.2020.00-16
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