Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management

Kelefouras, V, Keramidas, G and Voros, N (2017) Cache Partitioning + Loop Tiling: A Methodology for Effective Shared Cache Management. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2017). ISVLSI 2017, 03-05 Jul 2017, Bochum, Germany. IEEE , pp. 477-482. ISBN 9781509067626

Abstract

Metadata

Authors/Creators:
  • Kelefouras, V
  • Keramidas, G
  • Voros, N
Copyright, Publisher and Additional Information: (c) 2017, IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Dates:
  • Accepted: 25 April 2017
  • Published: 24 July 2017
Institution: The University of Leeds
Academic Units: The University of Leeds > Faculty of Engineering & Physical Sciences (Leeds) > School of Computing (Leeds)
Depositing User: Symplectic Publications
Date Deposited: 01 Sep 2017 10:31
Last Modified: 23 Jan 2018 18:23
Status: Published
Publisher: IEEE
Identification Number: https://doi.org/10.1109/ISVLSI.2017.89

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