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A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance

Robinson, M.P., Flintoft, I.D., Marvin, A.C. and Fischer, K. (2003) A simple model of EMI-induced timing jitter in digital circuits, its statistical distribution and its effect on circuit performance. IEEE Transactions on Electromagnetic Compatibility. pp. 513-519. ISSN 0018-9375

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Abstract

A simple model has been developed to characterize electromagnetic interference induced timing variations (jitter) in digital circuits. The model is based on measurable switching parameters of logic gates, and requires no knowledge of the internal workings of a device. It correctly predicts not only the dependence of jitter on the amplitude, modulation depth and frequency of the interfering signal, but also its statistical distribution. The model has been used to calculate the immunity level and bit error rate of a synchronous digital circuit subjected to radio frequency interference, and to compare the electromagnetic compatibility performance of fast and slow logic devices in such a circuit.

Item Type: Article
Copyright, Publisher and Additional Information: © 2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Keywords: digital circuits, immunity, jitter, radio frequency interference (RFI), statistical distribution, timing delays, PREDICTION, SYSTEMS
Academic Units: The University of York > Electronics (York)
Depositing User: Sherpa Assistant
Date Deposited: 16 Sep 2005
Last Modified: 17 Oct 2013 14:29
Published Version: http://dx.doi.org/10.1109/TEMC.2003.815529
Status: Published
Refereed: Yes
Related URLs:
URI: http://eprints.whiterose.ac.uk/id/eprint/640

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