Modelling framework for parallel SiC power MOSFETs chips in modules developed by planar technology

Kamel, T., Griffo, A. orcid.org/0000-0001-5642-2921 and Wang, J. (2019) Modelling framework for parallel SiC power MOSFETs chips in modules developed by planar technology. In: 2018 IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC). 2018 IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), 07-09 Nov 2018, Nottingham, United Kingdom. IEEE . ISBN 978-1-5386-4192-7

Abstract

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Authors/Creators:
Copyright, Publisher and Additional Information: © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works. Reproduced in accordance with the publisher's self-archiving policy.
Keywords: SiC Power MOSFET; Modelling; Parallel Chips per Switch; Planar Technology
Dates:
  • Accepted: 2018
  • Published (online): 14 January 2019
  • Published: 14 January 2019
Institution: The University of Sheffield
Academic Units: The University of Sheffield > Faculty of Engineering (Sheffield) > Department of Electronic and Electrical Engineering (Sheffield)
Funding Information:
FunderGrant number
EUROPEAN COMMISSION - HORIZON 2020I2MPECT - 636170
Depositing User: Symplectic Sheffield
Date Deposited: 19 Dec 2018 13:24
Last Modified: 13 Mar 2019 15:22
Status: Published
Publisher: IEEE
Refereed: Yes
Identification Number: https://doi.org/10.1109/ESARS-ITEC.2018.8607625

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