Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA

Khan, Z-U-A. and Benaissa, M. (2015) Throughput/Area-efficient ECC Processor Using Montgomery Point Multiplication on FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs, 62 (11). pp. 1078-1082. ISSN 1549-7747

Abstract

Metadata

Authors/Creators:
  • Khan, Z-U-A.
  • Benaissa, M.
Copyright, Publisher and Additional Information: © 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.
Keywords: Efficiency; elliptic curve cryptography (ECC); field-programmable gate array (FPGA); point multiplication (PM); throughput per area (throughput/area)
Dates:
  • Published: 13 July 2015
  • Accepted: 6 July 2015
Institution: The University of Sheffield
Academic Units: The University of Sheffield > Faculty of Engineering (Sheffield) > Department of Electronic and Electrical Engineering (Sheffield)
Depositing User: Symplectic Sheffield
Date Deposited: 22 Jan 2016 16:05
Last Modified: 08 Mar 2016 14:34
Published Version: http://dx.doi.org/10.1109/TCSII.2015.2455992
Status: Published
Publisher: Institute of Electrical and Electronics Engineers
Refereed: Yes
Identification Number: https://doi.org/10.1109/TCSII.2015.2455992

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