Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration

Trefzer, Martin Albrecht orcid.org/0000-0002-6196-6832, Walker, James Alfred orcid.org/0000-0003-2174-7173, Bale, Simon Jonathan et al. (1 more author) (2015) Fighting stochastic variability in a D-type flip-flop with transistor-level reconfiguration. IET Computers and Digital Techniques. pp. 190-196. ISSN 1751-861X

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Authors/Creators:
Copyright, Publisher and Additional Information: This content is made available by the publisher under a Creative Commons CC-BY Licence
Keywords: flip-flops; MOSFET; field programmable gate arrays, intrinsic stochastic variability; integrated circuit emphasis; hardware VLSI prototype; gold standard simulations; transistor level configuration options; next-generation FPGA architecture; post-fabrication transistor-level optimisation; simulation program; operating point; field programmable gate array; multireconfigurable architecture; virtual prototype; gate level; digital array architecture; prefabrication verification; D-type flip-flop timing characteristics; programmable analogue architecture; statistically enhanced high performance metal gate MOSFET compact models; technology process; design optimisation case study; size 25 nm
Dates:
  • Published: July 2015
  • Published (online): 18 June 2015
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Electronic Engineering (York)
Depositing User: Pure (York)
Date Deposited: 28 Oct 2015 11:27
Last Modified: 13 Nov 2019 09:27
Published Version: https://doi.org/10.1049/iet-cdt.2014.0146
Status: Published
Refereed: Yes
Identification Number: https://doi.org/10.1049/iet-cdt.2014.0146
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Filename: IET_CDT.2014.0146.pdf

Description: IET-CDT.2014.0146

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