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Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture

Huibin, S., Bailey, C., Farrall, G., Hastie, N. and Jenkins, S. (2005) Combined Simulator Statistics and Block-Code Sampling to Study Performance Enhancement of Microarchitecture. In: Proceedings of IEEE International System-On-Chip Conference 2005. SOC Conference, 2005, 19-23 Sept. 2005, Washington, DC. , 33 - 36. ISBN 0-7803-9264-7

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Abstract

This paper presents a simple approach combining the statistics of simulation and block code sampling to study the performance enhancement of the microarchitecture with duplicated pipelines (enhanced microarchitectures). We collect the statistics from the simulation of EEMBC benchmark code on a TriCore™ 2.0 implementation and use them to sample blocks of code and simulate different enhanced microarchitectures. The new simulation results are used to analyse the performance benefits of each microarchitecture enhancement, which can narrow down the design space exploration.

Item Type: Proceedings Paper
Institution: The University of York
Academic Units: The University of York > Computer Science (York)
Depositing User: York RAE Import
Date Deposited: 06 Apr 2009 16:16
Last Modified: 06 Apr 2009 16:16
Published Version: http://dx.doi.org/10.1109/SOCC.2005.1554449
Status: Published
Identification Number: 10.1109/SOCC.2005.1554449
URI: http://eprints.whiterose.ac.uk/id/eprint/7350

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