Alli, S. and Bailey, C. (2004) Compiler-directed dynamic memory disambiguation for loop structures. In: Proceedings of Euromicro Symposium on Digital Systems. DSD 2004, 31 Aug -3 Sept 2004, Rennes. , pp. 130-134. ISBN 0-7695-2203-3
The increase in the latencies of memory operations can be attributed to the increasing disparity between the speeds of the processor and memory. This effect is compounded by the fact that superscalar processors may generate several memory operations in a clock cycle, whereas the memory system often only handles one memory operation at a time because caches should preferably be single ported. Thus, there may be several memory operations outstanding concurrently. Processors alleviate the effects of this restriction by issuing loads ahead of stores. However, the memory references must first be disambiguated in order to ensure correct execution of the program. This paper introduces a technique for disambiguating memory references dynamically. This technique enables the compiler to convey information about the program that is available at compile time but cannot be exploited fully due to practical limitations. The processor can then use this information to issue loads ahead of stores.
|Institution:||The University of York|
|Academic Units:||The University of York > Electronics (York)|
|Depositing User:||York RAE Import|
|Date Deposited:||20 Feb 2009 11:21|
|Last Modified:||27 Feb 2009 18:07|