White Rose University Consortium logo
University of Leeds logo University of Sheffield logo York University logo

MCGREP - A Predictable Architecture for Embedded Real-Time Systems

Whitham, J. and Audsley, N.C. (2006) MCGREP - A Predictable Architecture for Embedded Real-Time Systems. In: Proceedings of the 27th IEEE International Real-Time Systems Symposium. RTSS 06, December 05 - 08, 2006, Rio de Janeiro, Brazil. IEEE , 13 - 24. ISBN 0-7695-2761-2

Full text not available from this repository.

Abstract

Real-time systems design involves many important choices, including that of the processor. The fastest processors achieve performance by utilizing architectural features that make them unpredictable, leading to difficulties proving offline that application process deadlines will be met, in the worst-case. Utilizing slower, more predictable processors, may not provide sufficient instruction throughput to execute all required application processes. This exposes a key trade-off in processor selection for real-time systems: predictability versus instruction throughput. This paper proposes MCGREP, a novel CPU architecture that combines predictability, high instruction throughput and flexibility. MCGREP is entirely microprogrammed, with multiple execution units. Basic operation involves implementation of a conventional set of CPU instructions in microcode - MCGREP then executes object code suitably compiled. Advanced operation allows the application to dynamically load new microcode, enabling new application specific instructions to increase overall performance. MCGREP is implemented upon reconfigurable logic (FPGA) - an increasingly important platform for the embedded RTS. Custom microcode configurations for new instructions are generated from C source. MCGREP is shown to have performance comparable to two popular FPGA softcore CPUs (OpenRISC and Microblaze, the latter a commercial product). Flexibility is demonstrated by implementing an existing instruction set (OpenRISC) in microcode, with application-specific instructions to improve overall performance. As a further demonstration, predictable twolevel interrupt and synchronization mechanisms are programmed in microcode.

Item Type: Proceedings Paper
Institution: The University of York
Academic Units: The University of York > Computer Science (York)
Depositing User: York RAE Import
Date Deposited: 08 Apr 2009 15:32
Last Modified: 08 Apr 2009 15:32
Published Version: http://dx.doi.org/10.1109/RTSS.2006.28
Status: Published
Publisher: IEEE
Identification Number: 10.1109/RTSS.2006.28
URI: http://eprints.whiterose.ac.uk/id/eprint/6212

Actions (repository staff only: login required)