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Realistic Analysis of Limited Parallel Software / Hardware Implementations

Audsley, N.C. and Bletsas, K. (2004) Realistic Analysis of Limited Parallel Software / Hardware Implementations. In: Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium. RTAS 04, 25-28 May 2004, Toronto, Canada. , pp. 388-395.

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Abstract

Proposed real-time system implementations combine reconfigurable hardware (for speed-up) with processor-memory architectures. Such hardware can execute many functions in parallel, leading to a limited parallel system where a single software process can execute on the processor at any time, in parallel with a number of functions implemented on the reconfigurable hardware. This approach is not amenable to conventional fixed priority timing analysis, as fundamental assumptions are compromised, namely that of a critical instant. This paper describes generalised fixed priority timing analysis for limited parallel systems, illustrated by an example system utilising field programmable gate arrays as the reconfigurable hardware resource.

Item Type: Proceedings Paper
Institution: The University of York
Academic Units: The University of York > Computer Science (York)
Depositing User: York RAE Import
Date Deposited: 08 Apr 2009 15:44
Last Modified: 08 Apr 2009 15:44
Published Version: http://dx.doi.org/10.1109/RTTAS.2004.1317285
Status: Published
Identification Number: 10.1109/RTTAS.2004.1317285
URI: http://eprints.whiterose.ac.uk/id/eprint/6190

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