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An engineering process for the verification of real-time systems

Burns, A. and Lin, T. -M. (2006) An engineering process for the verification of real-time systems. Formal Aspects of Computing, 19 (1). pp. 111-136. ISSN 0934-5043

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Abstract

The complete verification of the timing properties of a large critical system cannot be undertaken in a single step or with a single method. In this paper we present a process that links together a number of techniques and approaches that cover all stages of development from requirements analysis to code testing. The key elements of the process are: a constrained form of timed automata that uses delay and deadline to define temporal behaviour, notions of rely and guarantee to cover temporal dependencies, model checking for design verification, SPARK and Ravenscar restrictions for programming, and scheduling and response time analysis for asserting implementation compliance. Extended examples of the use of the process are given.

Item Type: Article
Keywords: Scheduling analysis - Ravenscar profile - Model checking - UPPAAL - SPARK - Ada95 - Rely/guarantee conditions
Academic Units: The University of York > Computer Science (York)
Depositing User: York RAE Import
Date Deposited: 12 Aug 2009 13:02
Last Modified: 12 Aug 2009 13:02
Published Version: http://dx.doi.org/10.1007/s00165-006-0021-4
Status: Published
Publisher: Springer Science + Business Media
Identification Number: 10.1007/s00165-006-0021-4
URI: http://eprints.whiterose.ac.uk/id/eprint/6150

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