An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network

Johnson, Anju P. orcid.org/0000-0002-7017-1644, Halliday, David M. orcid.org/0000-0001-9957-0983, Millard, Alan G. orcid.org/0000-0002-4424-5953 et al. (6 more authors) (2017) An FPGA-based hardware-efficient fault-tolerant astrocyte-neuron network. In: 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016. 2016 IEEE Symposium Series on Computational Intelligence, SSCI 2016, 06-09 Dec 2016 IEEE , GRC .

Abstract

The human brain is structured with the capacity to repair itself. This plasticity of the brain has motivated researchers to develop systems which have similar capabilities of fault tolerance and self-repair. Recent research findings have proven that interactions between astrocytes and neurons can actuate brain-like self-repair in a bidirectionally coupled astrocyte-neuron system. This paper presents a hardware realization of the bio-inspired self-repair architecture on an FPGA. We also introduce a reduced architecture for an FPGA-based hardware-efficient fault-tolerant system. This is based on the principle of retrograde signaling in an astrocyte-neuron network by simplifying the calcium dynamics within the astrocyte. The hardware optimized implementation shows more than a 90% decrease in hardware utilization and proves an efficient implementation for a large-scale astrocyte-neuron network. An Average spike rate of 0:027 spikes per clock cycle were observed for both the proposed models of astrocytes in the case of 100% partial fault.