Homeostatic Fault Tolerance in Spiking Neural Networks : A Dynamic Hardware Perspective

Johnson, Anju Pulikkakudi orcid.org/0000-0002-7017-1644, Liu, Junxiu, Millard, Alan Gregory orcid.org/0000-0002-4424-5953 et al. (6 more authors) (2018) Homeostatic Fault Tolerance in Spiking Neural Networks : A Dynamic Hardware Perspective. Ieee transactions on circuits and systems i-Regular papers. 7995041. pp. 687-699. ISSN 1549-8328

Abstract

Metadata

Authors/Creators:
Keywords: FPGA, Self-repair, bio-inspired engineering, dynamic partial reconfiguration, fault tolerance, homeostasis, mixed-mode clock manager, phase locked loop
Dates:
  • Accepted: 5 July 2017
  • Published (online): 28 July 2017
  • Published: 1 February 2018
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Electronic Engineering (York)
Funding Information:
FunderGrant number
EPSRCEP/N007050/1
Depositing User: Pure (York)
Date Deposited: 17 Aug 2017 13:15
Last Modified: 06 Dec 2023 12:01
Published Version: https://doi.org/10.1109/TCSI.2017.2726763
Status: Published
Refereed: Yes
Identification Number: https://doi.org/10.1109/TCSI.2017.2726763
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Description: Homeostatic Fault Tolerance in Spiking Neural Networks: A Dynamic Hardware Perspective

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