Items where authors include "Jiang, Yu"

Article

Huang, Jing, Li, Renfa, Jiao, Xun et al. (2 more authors) (2020) Dynamic DAG Scheduling on Multiprocessor Systems: Reliability, Energy and Makespan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (In Press)

Gao, Jian, Xu, Yiwen, Jiang, Yu et al. (4 more authors) (2020) EM-Fuzz: Augmented Firmware Fuzzing via Memory Checking. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (In Press)

Jiao, Xun, Ma, Dongning, Chang, Wanli orcid.org/0000-0002-4053-8898 et al. (1 more author) (2020) LEVAX : An Input-Aware Learning-Based Error Model of Voltage-Scaled Functional Units. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (In Press)

Proceedings Paper

Dai, Xiaotian orcid.org/0000-0002-6669-5234, Zhao, Shuai, Jiang, Yu et al. (3 more authors) (2020) Fixed-Priority Scheduling and Controller Co-Design for Time-Sensitive Networks. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2020). UNSPECIFIED. IEEE .

Luo, Zhengxiong, Zuo, Feilong, Shen, Yuheng et al. (3 more authors) (2020) ICS protocol fuzzing: Coverage guided packet crack and generation. In: Design Automation Conference (DAC). UNSPECIFIED. . (In Press)

Jiao, Xun, Ma, Dongning, Chang, Wanli orcid.org/0000-0002-4053-8898 et al. (1 more author) (2020) TEVoT: Timing error modeling of functional units under dynamic voltage and temperature variations. In: Design Automation Conference (DAC). UNSPECIFIED. . (In Press)