High Speed and Low Latency ECC Implementation over GF(2m) on FPGA

Khan, Z.U.A. and Benaissa, M. (2017) High Speed and Low Latency ECC Implementation over GF(2m) on FPGA. IEEE Transactions on Very Large Scale Integration Systems, 25 (1). pp. 165-176. ISSN 1557-9999

Abstract

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Authors/Creators:
  • Khan, Z.U.A.
  • Benaissa, M.
Copyright, Publisher and Additional Information: © 2016 IEEE. This is an author produced version of a paper subsequently published in IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Uploaded in accordance with the publisher's self-archiving policy.
Dates:
  • Accepted: 8 May 2016
  • Published (online): 14 June 2016
  • Published: January 2017
Institution: The University of Sheffield
Academic Units: The University of Sheffield > Faculty of Engineering (Sheffield) > Department of Electronic and Electrical Engineering (Sheffield)
Depositing User: Symplectic Sheffield
Date Deposited: 10 May 2016 09:30
Last Modified: 18 Jul 2017 08:39
Published Version: http://dx.doi.org/10.1109/TVLSI.2016.2574620
Status: Published
Publisher: IEEE
Refereed: Yes
Identification Number: https://doi.org/10.1109/TVLSI.2016.2574620

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