Bailey, C. (2004) A proposed mechanism for super-pipelined instruction-issue for ILP stack. In: Proceedings of Euromicro Symposium on Digital Systems. DSD 2004, 31 Aug.-3 Sept. 2004, Rennes. , pp. 121-129. ISBN 0-7695-2203-3
A resurgence of interest in hardware stack-machine architectures, in which an implicitly addressed operand stack mode of computation is used, has followed closely in the wake of the growth of Java technology. However hardware for direct execution of stack-based machine level operations suffer from a lack of development in areas of advanced machine architecture, in particular where instruction-level parallelism is concerned. In this paper the author proposes a mechanism for super-pipelined issue of stack-based instructions to support an in-order issue policy with out-of-order completion, and introduces some preliminary results in order to illustrate possible trade-offs and issues likely to be valuable focal points for a full performance assessment in future work.
|Institution:||The University of York|
|Academic Units:||The University of York > Computer Science (York)|
|Depositing User:||York RAE Import|
|Date Deposited:||07 Apr 2009 09:31|
|Last Modified:||07 Apr 2009 09:31|