Kennedy, J.V., Austin, J. orcid.org/0000-0001-5762-8614, Pack, R. et al. (1 more author) (1995) C-NNAP - A parallel processing architecture for binary neural networks. In: Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE , New York , pp. 1037-1041.
This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations.
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|Institution:||The University of York|
|Academic Units:||The University of York > Computer Science (York)|
|Depositing User:||Repository Assistant|
|Date Deposited:||03 Jan 2007|
|Last Modified:||07 Jan 2017 14:28|