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C-NNAP - A parallel processing architecture for binary neural networks

Kennedy, J.V., Austin, J., Pack, R. and Cass, B. (1995) C-NNAP - A parallel processing architecture for binary neural networks. In: Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE , New York , pp. 1037-1041. ISBN 0780327691

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Abstract

This paper describes the CNNAP machine, a MIMD implementation of an array of ADAM binary neural networks, primarily designed for image processing. CNNAP comprises an array of VME cards each containing a DSP, SCSI controller, and a new design of the SAT peripheral processor. The SAT processor is a dedicated hardware implemention that performs binary neural network computations. The SAT processor yields a potential speed-up of between 108 times to 182 times that of the current DSP with its dedicated coprocessor. CNNAP in association with the SAT provides a fast, parallel environment for performing binary neural network operations.

Item Type: Book Section
Copyright, Publisher and Additional Information: © 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Academic Units: The University of York > Computer Science (York)
Depositing User: Repository Assistant
Date Deposited: 03 Jan 2007
Last Modified: 17 Oct 2013 15:18
Published Version: http://dx.doi.org/10.1109/ICNN.1995.487564
Status: Published
Publisher: IEEE
Refereed: No
Related URLs:
URI: http://eprints.whiterose.ac.uk/id/eprint/1870

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