C-NNAP - A parallel processing architecture for binary neural networks

Kennedy, J.V., Austin, J. orcid.org/0000-0001-5762-8614, Pack, R. and Cass, B. (1995) C-NNAP - A parallel processing architecture for binary neural networks. In: Proceedings of the IEEE International Conference on Neural Networks (ICNN 95). (University of Western Australia, Perth, Australia, Nov 27-Dec 01, 1995). IEEE , New York , pp. 1037-1041. ISBN 0780327691



Copyright, Publisher and Additional Information: © 1995 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.
Institution: The University of York
Academic Units: The University of York > Computer Science (York)
Depositing User: Repository Assistant
Date Deposited: 03 Jan 2007
Last Modified: 02 Jun 2016 15:56
Published Version: http://dx.doi.org/10.1109/ICNN.1995.487564
Status: Published
Publisher: IEEE
Refereed: No


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