An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

Johnson, Anju P. orcid.org/0000-0002-7017-1644, Chakraborty, Rajat Subhra and Mukhopadhyay, Debdeep (2016) An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA. IEEE Transactions on Circuits and Systems II: Express Briefs. pp. 452-456. ISSN 1549-7747

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Copyright, Publisher and Additional Information: (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. This is an author-produced version of the published paper. Uploaded in accordance with the publisher’s self-archiving policy. Further copying may not be permitted; contact the publisher for details
Keywords: Digital Clock Manager,Dynamic Partial Reconfiguration,field programmable gate arrays (FPGAs),True Random Number Generators
Dates:
  • Published: 10 May 2016
Institution: The University of York
Academic Units: The University of York > Faculty of Sciences (York) > Electronic Engineering (York)
Depositing User: Pure (York)
Date Deposited: 12 Aug 2016 11:34
Last Modified: 14 Jul 2019 00:53
Published Version: https://doi.org/10.1109/TCSII.2016.2566262
Status: Published
Refereed: Yes
Identification Number: https://doi.org/10.1109/TCSII.2016.2566262

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Description: An Improved DCM-based Tunable True Random Number Generator for Xilinx FPGA

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